FIG. 1 is a functional block diagram of a conventional flash memory system 1. The core of memory system 1 is an array 12 of flash memory cells. The individual cells in array 12 are arranged in rows and columns, with there being, for example, a total of 256 K eight bit words in array 12. The individual memory cells (not shown) are accessed by using an eighteen bit address A0-A17, which is input by means of address pins 13. Nine of the eighteen address bits are used by X decoder 14 to select the row of array 12 in which a desired memory cell is located, and the remaining nine bits are used by Y decoder 16 to select the appropriate column of array 12 in which the desired cell is located.
Memory system 1 contains an internal state machine (ISM) 20 which controls the data processing operations performed on memory array 12, such as the steps necessary for carrying out programming, reading and erasing operations for the memory cells of array 12. State machine 20 functions to reduce the overhead required of an external processor (not depicted) typically used in association with memory system 1.
For example, if memory cell array 12 is to be erased (typically, all or large blocks of cells are erased at the same time), the external processor causes the output enable pin OE to be inactive (high), and the chip enable CE and write enable WE pins to be active (low). The processor then issues an 8 bit command 20H (0010 0000) on data I/O pins 15 (DQ0-DQ7), typically called an Erase Setup command. This is followed by the issuance of a second eight bit command D0H (1101 0000), typically called an Erase Confirm command. Two separate commands are used to initiate the erase operation so as to minimize the possibility of inadvertently beginning an erase procedure.
The commands issued on I/O pins 15 are transferred to data input buffer 22 and then to command execution logic unit 24. Command execution logic unit 24 receives and interprets the commands used to instruct state machine 20 to perform the steps required for erasing array 12 or carrying out another desired operation. Once the erase sequence is completed, state machine 20 updates 8 bit status register 26. The contents of status register 26 is transferred to data output buffer 28, which makes the contents available on data I/O pins 15 of memory system 1. Status register 26 permits the external processor to monitor the status of state machine 20 during memory array write and erase operations. The external processor periodically polls data I/O pins 15 to read the contents of status register 26 in order to determine whether an erase sequence (or other operation) has been completed and whether the operation was successful.
As noted, the contents of status register 26 provides information to a user of memory system 1 concerning the internal operation of the memory system. This information includes the status (ready or busy) of state machine 20, whether an erase or write operation has been successful, whether an erase operation has been suspended, and whether the write/erase supply voltage (Vpp) is present.
FIG. 2 is a block diagram of the components of memory system 1 of FIG. 1 which are used in writing data to and reading data from a memory cell contained in array 12, and in reading the contents of status register 26. As shown in FIG. 2, an input/output (data) pad 40 is connected to circuit elements which form a data read path 42 and a data write path 44 to memory array 12. Pad 40 is part of the metallization of the integrated circuit containing the memory array and is connected by a wire bond or other means to a data pin of the integrated circuit package.
Read path 42 and write path 44 are electrically connected to data line 46, which connects those paths to memory array 12 by means of decoder or multiplexer 16. Note that in FIG. 2, only Y decoder 16 is shown. Similarly, only the columns of array 12 are indicated. However, as shown in FIG. 1, X decoder 14 which connects to the rows of array 12 is also part of memory system 1. Thus, both X decoder 14 and the rows of array 12 could typically be shown in a more complete diagram of the components.
Write path 44 typically includes a data latch (not shown) for storing data input by means of pad 40. The data latch is activated or enabled by a latch enable signal. The latched data is sent to data input buffer 48, which produces the voltage on line 50 which is applied to a memory cell in order to program the cell. Input buffer 48 is typically implemented in the form of a tri-statable driver having an output which can be placed in a high impedance mode and effectively disabled during a read (or other non-programming) operation. The disabling of input buffer 48 is achieved by means of tri-state control line 49. In some implementations, the functions of the latch and input buffer 48 may be combined into a single device. A latch element is used so that the input/output pins can be used for other functions after the programming signals are input and while the signals are being processed by elements of the data write circuit.
When reading a memory cell of array 12, decoder (multiplexer) 16 is again used to access the desired memory cell in the array. In the event the cell being read is in an erased state, the cell will conduct a current which is converted to a voltage along line 46. Sense amplifier 52 is used to determine the state of the cell, i.e., whether it is programmed or erased (corresponding to a binary value of 0 or 1, respectively), and is enabled by means of sense amplifier enable signal 54. The state of a memory cell is determined by comparing the voltage on data line 46 to a reference voltage. The outcome of this comparison between the two input voltages is an output which is either high or low, corresponding to a digital value of one or zero.
The output of sense amplifier 52 is sent to output buffer 56 which drives the data to output pad 40, where it is accessed by a user. Output buffer 56 is enabled by means of output enable signal 57. It is noted that a typical memory system would contain an input buffer, output buffer, sense amplifier, and data read and data write path of the type shown in FIG. 2 for each input/output pin 15 of FIG. 1.
When the external processor polls status register 26 to determine the status of a read or write operation, sense amplifier enable signal 54 is used to disable sense amplifier 52 by taking that node to a high impedance. Status register enable signal 27, which is typically at a high impedance value during a read operation, is then used to enable a read of status register 26 and to route the contents of status register 26 to pad 40. As previously mentioned pad 40 is connected to an input/output pin 15 of FIG. 1.
However, the information provided by status register 26 is indicative of only a small subset of the signals generated during the operation of memory system 1. Other internal signals and data indicative of the operating status or state of the memory system are generated during different stages of the read, erase, and programming operations. This information can be used by a memory chip designer to determine at which stage of operation an error occurred, thereby causing a malfunction of the memory device.
Although these internal signals and data are of use in determining the cause of a device failure, this information cannot be readily accessed in most memory systems. One means for accessing the signals is to open up the memory package and use a probe to read the signals generated at various points in the device as the device cycles through its operations. This process is referred to as micro-probing of the device. However, micro-probing is of limited use in investigating a failed memory device inside a package because memory system dies inside a package generally have a layer of passivation glass deposited on them. This prevents successful micro-probing of the device even if the package is opened.
What is desired is a memory system in which the cause of a device failure or operational error can be determined with greater accuracy than is possible with presently available systems. This and other advantages of the present invention will be apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.